1. Field of the Invention
The present invention relates to a system and method for ATM (Asynchronous Transfer Mode) data transmission, and more particularly to a data transmission system and method using an ATM segmentation device in which an ATM cell transmission timing signal is generated from a real-time data.
2. Description of the Related Art
These years, the asynchronous transfer mode (ATM) data transmission has actively been researched and developed for a digital communication in the fields of fast broad-band communications and broad-band ISDN (B-ISDN).
An ATM communication network comprises ATM transmitters and ATM exchanges to which ATM terminals are connected. The ATM terminal segments an information into packets of a fixed length (53 bytes) called "ATM cell" for transmission. Each of the ATM cells consists of a 5-byte header and a 48-byte payload. A sequence No., virtual channel No., etc. are written in the header, and an information to be transmitted is written in the payload. When there is much information to be transmitted by the ATM terminal of this data transmission system, the ATM terminal segments the information into a plurality of ATM cells (will also be referred to simply as "cell or cells" hereinafter) for transmission. However, when the ATM terminal has no information to transmit, it will transmit no cell. Also, the ATM transmitter is capable of transmitting, over a same transmission channel, cells transmitted from transmitting terminals of different transmission rates. The ATM receiving terminal restores an original information based on the content of the header of each received cell. Thus, the ATM transmitter has no frame period characterizing the conventional STM (Synchronous Transfer Mode) but transmits a single cell or a plurality of cells at random.
FIG. 1 shows a conventional data transmission system. In FIG. 1, an ATM data transmitter incorporated in each ATM transmitting terminal is generally indicated with a reference 101. The ATM transmitter 101 comprises a data buffer 102 consisting of DRAM, etc., an ATM segmentation block 105 including an ATM cell generation circuit 103 and a transmission VC (Virtual Channel) selection circuit 104, a physical layer device 106 and the like disposed downstream of the ATM segmentation block 105.
The data buffer 102 stores various data as data to be transmitted. The ATM cell generation circuit 103 of the ATM segmentation block 105 reads to-be-transmitted data stored in the data buffer 102 to generate an aforementioned 53-byte cell. The transmission VC selection circuit 104 determines a virtual channel over which each is transmitted. Also, the transmission VC selection circuit 104 incorporates a traffic shaver circuit (not illustrated) to adjust the transmission rate for each cell.
The ATM segmentation block 105 is connected to a CPU (not illustrated). The transmission VC selection circuit 104 determines a virtual channel over which a cell is to be transmitted, based on a transfer rate predetermined by the CPU, and the traffic shaver circuit will determine a time when the cell is to be transmitted. Based on the results of the above, the ATM cell generation circuit 103 reads to-be-transmitted data stored in the data buffer 102 and segments it into payloads each of 48 bytes. Further, the ATM cell generation circuit 103 write a virtual channel No., etc. as a 5-byte header for each payload to generate 53-byte cells each of which will be supplied to the physical layer device 106 via a UTOPIA (Universal Test & Operation Physical Interface for ATM) interface, etc.
The physical layer device 106 processes each received cell in a manner depending upon a certain physical layer, and then supplies it to an optical fiber (not illustrated), for example. Thus, each cell is transmitted through the optical fiber to an ATM network, and supplied to another ATM terminal via an ATM exchange (not illustrated).
The data transmitter 101 uses the above-mentioned traffic shaver circuit of the transmission VC selection circuit 104 to determine a time when a cell is to be transmitted based on a transfer rate designated by the CPU, without discrimination of the quality of to-be-transmitted data, for example, whether the data is a real-time data or a nonreal-time data.
However, the clock system for the real-time data is different from that for ATM clock system, so it is technically impossible to completely eliminate the difference between these clock systems at the time of data transmission. Therefore, the conventional data transmitter 101 is disadvantageous in that when there are both real-time data and nonreal-time data to be transmitted to outside from the physical layer device 106, an excess or shortage of data takes place due to such difference in clock system at the time of transmission even if a same transmission rate is set for both the real-time and nonreal-time data.
Furthermore, for connection of various systems which supply real-time data as mentioned above to the conventional data transmitter 101 needs a unique adjustment for each of the systems.